Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version2405991
date_generatedThu Apr 22 10:58:24 2021 os_platformLIN64
product_versionVivado v2018.3 (64-bit) project_idbfa302e43c0949fea4fe564a8cb8220b
project_iteration3 random_id76d4af5be67a5c9d86550762f9e5af9a
registration_id76d4af5be67a5c9d86550762f9e5af9a route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i3 CPU M 330 @ 2.13GHz cpu_speed1249.013 MHz
os_nameUbuntu os_releaseUbuntu 20.04.2 LTS
system_ram4.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_remove_selected_elements=1 basedialog_cancel=14 basedialog_ok=32 boardchooser_board_table=6
closeplanner_no=1 cmdmsgdialog_ok=3 constraintschooserpanel_create_file=2 createconstraintsfilepanel_file_name=2
createsrcfiledialog_file_name=5 filesetpanel_file_set_panel_tree=147 flownavigatortreepanel_flow_navigator_tree=24 gettingstartedview_create_new_project=1
gettingstartedview_open_project=2 hardwaredeviceproppanels_specify_bitstream_file=2 hardwaretreepanel_hardware_tree_table=11 mainmenumgr_checkpoint=5
mainmenumgr_design_hubs=2 mainmenumgr_export=6 mainmenumgr_file=12 mainmenumgr_help=4
mainmenumgr_ip=5 mainmenumgr_open_recent_project=1 mainmenumgr_project=7 mainmenumgr_text_editor=5
maintoolbarmgr_open=1 maintoolbarmgr_run=7 mainwintoolbarmgr_select_or_save_window_layout=2 opentargetwizard_connect_to=4
pacommandnames_add_design_tools=2 pacommandnames_add_sources=6 pacommandnames_add_xvc_target=1 pacommandnames_auto_connect_target=12
pacommandnames_auto_update_hier=9 pacommandnames_close_project=1 pacommandnames_create_svf_target=1 pacommandnames_impl_settings=1
pacommandnames_open_hardware_manager=2 pacommandnames_open_project=1 pacommandnames_open_target_wizard=3 pacommandnames_program_fpga=1
pacommandnames_refresh_server=2 pacommandnames_run_bitgen=4 pacommandnames_run_implementation=1 pacommandnames_run_synthesis=4
pacommandnames_save_project_as=1 paviews_project_summary=3 paviews_schematic=1 paviews_tcl_object_view=2
programdebugtab_open_target=11 programdebugtab_program_device=1 programfpgadialog_program=2 projectdashboardview_dashboard=1
projectdashboardview_tabbed_pane=1 projectnamechooser_project_name=1 projecttab_close_design=1 rdicommands_delete=1
rdicommands_properties=1 rdicommands_save_file=1 rdicommands_settings=1 rungadget_show_warning_and_error_messages_in_messages=4
saveprojectutils_save=1 settingsdialog_options_tree=3 settingsdialog_project_tree=6 settingsprojectgeneralpage_choose_device_for_your_project=2
srcchooserpanel_add_or_create_source_file=3 srcchooserpanel_change_source_properties=1 srcchooserpanel_create_file=5 srcchoosertable_src_chooser_table=5
srcmenu_ip_hierarchy=10 syntheticagettingstartedview_recent_projects=1 tclobjecttreetable_treetable=10 tclobjectview_reset_properties=1
java_command_handlers
adddesigntools=2 addsources=6 addxvctarget=1 autoconnecttarget=12
closeproject=1 createblockdesign=1 createsvftarget=1 editdelete=1
editproperties=1 exitapp=2 fliptoviewtaskimplementation=1 launchopentarget=3
launchprogramfpga=2 newproject=1 openhardwaremanager=6 openproject=3
openrecenttarget=4 programdevice=1 refreshserver=2 runbitgen=5
runimplementation=5 runschematic=2 runsynthesis=7 saveprojectas=1
showview=3 toolssettings=5 viewlayoutcmd=2 viewtaskimplementation=2
viewtaskprogramanddebug=1 viewtasksynthesis=1
other_data
guimode=6
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
ibuf=4 obuf=4
pre_unisim_transformation
ibuf=4 obuf=4

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
zps7-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=0 bufgctrl_util_percentage=0.00
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=280 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
ibuf_functional_category=IO ibuf_used=4 obuf_functional_category=IO obuf_used=4
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=0 lut_as_logic_util_percentage=0.00
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=0 register_as_flip_flop_util_percentage=0.00
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=0 slice_luts_util_percentage=0.00
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=0 slice_registers_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=0 lut_as_logic_util_percentage=0.00 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0 register_driven_from_outside_the_slice_used=0 register_driven_from_within_the_slice_fixed=0 register_driven_from_within_the_slice_used=0
slice_available=13300 slice_fixed=0 slice_registers_available=106400 slice_registers_fixed=0
slice_registers_used=0 slice_registers_util_percentage=0.00 slice_used=0 slice_util_percentage=0.00
slicel_fixed=0 slicel_used=0 slicem_fixed=0 slicem_used=0
unique_control_sets_available=13300 unique_control_sets_fixed=13300 unique_control_sets_used=0 unique_control_sets_util_percentage=0.00
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z020clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=button_led -verilog_define=default::[not_specified]
usage
elapsed=00:00:32s hls_ip=0 memory_gain=382.828MB memory_peak=1706.152MB