p_1_or Project Status (05/14/2021 - 12:13:59)
Project File: Vhdl_p1.xise Parser Errors: No Errors
Module Name: p_1_or Implementation State: Placed and Routed
Target Device: xc3s1200e-5fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 1 17,344 1%  
Number of occupied Slices 1 8,672 1%  
    Number of Slices containing only related logic 1 1 100%  
    Number of Slices containing unrelated logic 0 1 0%  
Total Number of 4 input LUTs 1 17,344 1%  
Number of bonded IOBs 3 250 1%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri May 14 12:13:13 2021000
Translation ReportCurrentFri May 14 12:13:23 2021000
Map ReportCurrentFri May 14 12:13:35 2021002 Infos (2 new)
Place and Route ReportCurrentFri May 14 12:13:53 2021001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri May 14 12:13:57 2021006 Infos (6 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 05/14/2021 - 12:13:59