//https://edaplayground.com/
//podesavanja
//Testbench + Design   System Verilog/verilog
//UVM/OVM              None
// Tools @ Simulators  Icarus Verilog 0.9.7


// Code your design here
module abc(y,a,b);
  input a,b;
  output y;
  
  assign y=a&b;
endmodule



// Code your testbench here
// or browse Examples
module tb;
  
  wire y;
  reg a, b;
  abc a1(y,a,b);
  
  initial
    begin
      a=1'b0; b=1'b0;
      #10 a=1'b0; b=1'b1;
      #10 a=1'b1; b=1'b0;
      #10 a=1'b1; b=1'b1;
    end
  initial
    $monitor($time, "a=%b,b=%b, y=%b",a,b,y);
  initial
    begin
      $dumpfile("dump.vcd"); $dumpvars(1);
  	end
  
endmodule



drugi
/
// Company: 
// Engineer: 
// 
// Create Date:    10:19:16 10/10/2016 
// Design Name: 
// Module Name:    polusabirac 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module polusabirac(x, y, s, c);
   input x, y;
   output s, c;
   xor(s, x, y);
   and(c, x, y); 

endmodule
// Code your testbench here
// or browse Examples
module tb2;
  
  wire s,c;
  reg x, y;
  polusabirac a1(x, y, s, c);
  
  initial
    begin
      x=1'b0; y=1'b0;
      #10 x=1'b0; y=1'b1;
      #10 x=1'b1; y=1'b0;
      #10 x=1'b1; y=1'b1;
    end
  initial
    $monitor($time, "x=%b,y=%b, s=%b, c=%b",x,y,s,c);
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(1);
  	end
  
endmodule