| Zadatak1 Project Status | |||
| Project File: | Zadatak1.xise | Parser Errors: | No Errors |
| Module Name: | Zadatak1 | Implementation State: | Synthesized |
| Target Device: | xc3s1200e-5fg320 |
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No Errors |
| Product Version: | ISE 14.7 |
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No Warnings |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slices | 1 | 8672 | 0% | |
| Number of 4 input LUTs | 1 | 17344 | 0% | |
| Number of bonded IOBs | 5 | 250 | 2% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Mon Aug 30 03:33:42 2021 | 0 | 0 | 0 | |
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Mon Aug 30 03:33:42 2021 | |