Zadatak1 Project Status
Project File: Zadatak1.xise Parser Errors: No Errors
Module Name: Zadatak1 Implementation State: Synthesized
Target Device: xc3s1200e-5fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 1 8672 0%
Number of 4 input LUTs 1 17344 0%
Number of bonded IOBs 5 250 2%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Aug 30 03:33:42 2021000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMon Aug 30 03:33:42 2021

Date Generated: 04/29/2022 - 08:11:13