RegisterFile Project Status
Project File: Reg_3.xise Parser Errors: X 1 Error
Module Name: RegisterFile Implementation State: New
Target Device: xa95*xl-**
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
CPLD Fitter Report (Text)     
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 04/29/2022 - 23:05:42