| Mux_4_1_case Project Status (10/31/2016 - 09:29:04) | |||
| Project File: | Mux_case.xise | Parser Errors: | X 2 Errors |
| Module Name: | Mux_4_1_case | Implementation State: | Placed and Routed |
| Target Device: | xc3s1200e-5ft256 |
|
No Errors |
| Product Version: | ISE 14.7 |
|
No Warnings |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
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|
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of 4 input LUTs | 2 | 17,344 | 1% | ||
| Number of occupied Slices | 1 | 8,672 | 1% | ||
| Number of Slices containing only related logic | 1 | 1 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 1 | 0% | ||
| Total Number of 4 input LUTs | 2 | 17,344 | 1% | ||
| Number of bonded IOBs | 7 | 190 | 3% | ||
| Average Fanout of Non-Clock Nets | 1.14 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Mon Oct 31 09:28:27 2016 | 0 | 0 | 0 | |
| Translation Report | Current | Mon Oct 31 09:28:35 2016 | 0 | 0 | 0 | |
| Map Report | Current | Mon Oct 31 09:28:41 2016 | 0 | 0 | 2 Infos (2 new) | |
| Place and Route Report | Current | Mon Oct 31 09:28:58 2016 | 0 | 0 | 1 Info (1 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Mon Oct 31 09:29:02 2016 | 0 | 0 | 6 Infos (6 new) | |
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |