Log_4_input Project Status (10/31/2016 - 08:48:08)
Project File: Gate_top_model.xise Parser Errors: No Errors
Module Name: Log_4_input_top Implementation State: Placed and Routed
Target Device: xc3s1200e-5ft256
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 3 17,344 1%  
Number of occupied Slices 2 8,672 1%  
    Number of Slices containing only related logic 2 2 100%  
    Number of Slices containing unrelated logic 0 2 0%  
Total Number of 4 input LUTs 3 17,344 1%  
Number of bonded IOBs 7 190 3%  
Average Fanout of Non-Clock Nets 2.14      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Oct 31 08:47:17 2016000
Translation ReportCurrentMon Oct 31 08:47:29 2016000
Map ReportCurrentMon Oct 31 08:47:41 2016002 Infos (2 new)
Place and Route ReportCurrentMon Oct 31 08:48:01 2016001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Oct 31 08:48:06 2016006 Infos (6 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/31/2016 - 08:48:08