Log_4_input Project Status (10/31/2016 - 08:48:08)
Project File:	Gate_top_model.xise	Parser Errors:	No Errors
Module Name:	Log_4_input	Implementation State:	Placed and Routed
Target Device:	xc3s1200e-5ft256	Errors:
Product Version:	ISE 14.7	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 10/31/2016 - 08:48:08