module alu(
    input wire [7:0] A,
    input wire [7:0] B,
    input wire [2:0] sel,
    output reg [7:0] Y,
    output wire zero,
    output reg carry
);

    always @(*) begin
        carry = 1'b0;

        case (sel)
            3'b000: {carry, Y} = A + B;   // sabiranje
            3'b001: {carry, Y} = A - B;   // oduzimanje
            3'b010: Y = A & B;            // AND
            3'b011: Y = A | B;            // OR
            3'b100: Y = A ^ B;            // XOR
            3'b101: Y = ~A;               // NOT A
            3'b110: Y = A << 1;           // shift levo
            3'b111: Y = A >> 1;           // shift desno
            default: Y = 8'd0;
        endcase
    end

    assign zero = (Y == 8'd0);

endmodule