module registri(
    input wire clk,
    input wire rst,
    input wire we,
    input wire [1:0] addr,
    input wire [7:0] din,
    output reg [7:0] dout
);

    reg [7:0] R0;
    reg [7:0] R1;
    reg [7:0] R2;
    reg [7:0] R3;

    always @(posedge clk) begin
        if (rst) begin
            R0 <= 8'd0;
            R1 <= 8'd0;
            R2 <= 8'd0;
            R3 <= 8'd0;
        end else begin
            if (we) begin
                case (addr)
                    2'b00: R0 <= din;
                    2'b01: R1 <= din;
                    2'b10: R2 <= din;
                    2'b11: R3 <= din;
                endcase
            end
        end
    end

    always @(*) begin
        case (addr)
            2'b00: dout = R0;
            2'b01: dout = R1;
            2'b10: dout = R2;
            2'b11: dout = R3;
            default: dout = 8'd0;
        endcase
    end

endmodule