`timescale 1ns/1ps

module registri_tb;

    reg clk;
    reg rst;
    reg we;
    reg [1:0] addr;
    reg [7:0] din;
    wire [7:0] dout;

    // instanca modula
    registri uut (
        .clk(clk),
        .rst(rst),
        .we(we),
        .addr(addr),
        .din(din),
        .dout(dout)
    );

    // clock generator (period 10ns)
    always #5 clk = ~clk;

    initial begin
        // inicijalizacija
        clk = 0;
        rst = 1;
        we = 0;
        addr = 0;
        din = 0;

        // reset
        #10;
        rst = 0;

        // upis u R0
        #10;
        we = 1;
        addr = 2'b00;
        din = 8'hAA;

        // upis u R1
        #10;
        addr = 2'b01;
        din = 8'h55;

        // čitanje R0
        #10;
        we = 0;
        addr = 2'b00;

        // čitanje R1
        #10;
        addr = 2'b01;

        // upis u R2
        #10;
        we = 1;
        addr = 2'b10;
        din = 8'hF0;

        // čitanje R2
        #10;
        we = 0;
        addr = 2'b10;

        #20;
        $stop;
    end

endmodule