top Project Status
Project File: Instanicranje_modula.xise Parser Errors: No Errors
Module Name: top Implementation State: Placed and Routed
Target Device: xc3s100e-5vq100
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 4 1,920 1%  
Number of occupied Slices 4 960 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 4 1,920 1%  
Number of bonded IOBs 12 66 18%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Oct 26 09:56:34 2023000
Translation ReportCurrentThu Oct 26 09:56:40 2023000
Map ReportCurrentThu Oct 26 09:56:48 2023002 Infos (0 new)
Place and Route ReportCurrentThu Oct 26 09:56:56 2023001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Oct 26 09:56:58 2023006 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu Oct 26 09:59:38 2023

Date Generated: 10/26/2023 - 14:53:23