`timescale 1ns/1ps

module tb_counter_4bit_jk;

reg clk;
reg preset;
reg clear;

wire q0;
wire q1;
wire q2;
wire q3;

counter_4bit_jk uut (
    .clk(clk),
    .preset(preset),
    .clear(clear),
    .q0(q0),
    .q1(q1),
    .q2(q2),
    .q3(q3)
);

// generator takta
initial begin
    clk = 0;
    forever #10 clk = ~clk;
end

// pobudni signali
initial begin
    preset = 0;
    clear  = 1;
    
    #30;
    preset = 1;   // izlazak iz preset stanja

    #200;
    clear = 0;    // asinhroni clear

    #20;
    clear = 1;    // nastavak brojanja

    #300;
    $stop;
end

endmodule