| kolo_1 Project Status | |||
| Project File: | Prvi_primer.xise | Parser Errors: | No Errors |
| Module Name: | kolo_1 | Implementation State: | Placed and Routed |
| Target Device: | xc3s1200e-5fg320 |
|
No Errors |
| Product Version: | ISE 14.7 |
|
No Warnings |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of 4 input LUTs | 1 | 17,344 | 1% | ||
| Number of occupied Slices | 1 | 8,672 | 1% | ||
| Number of Slices containing only related logic | 1 | 1 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 1 | 0% | ||
| Total Number of 4 input LUTs | 1 | 17,344 | 1% | ||
| Number of bonded IOBs | 4 | 250 | 1% | ||
| Average Fanout of Non-Clock Nets | 1.00 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Wed Apr 5 15:28:08 2017 | 0 | 0 | 0 | |
| Translation Report | Current | Wed Apr 5 15:28:22 2017 | 0 | 0 | 0 | |
| Map Report | Current | Wed Apr 5 15:28:36 2017 | 0 | 0 | 2 Infos (0 new) | |
| Place and Route Report | Current | Wed Apr 5 15:28:58 2017 | 0 | 0 | 1 Info (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Wed Apr 5 15:29:04 2017 | 0 | 0 | 6 Infos (0 new) | |
| Bitgen Report | Out of Date | Tue Apr 4 11:50:42 2017 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | Wed Mar 24 09:44:58 2021 | |
| WebTalk Report | Out of Date | Tue Apr 4 11:50:42 2017 | |
| WebTalk Log File | Out of Date | Tue Apr 4 11:50:50 2017 | |