kolo_1 Project Status
Project File: Prvi_primer.xise Parser Errors: No Errors
Module Name: kolo_1 Implementation State: Placed and Routed
Target Device: xc3s1200e-5fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 1 17,344 1%  
Number of occupied Slices 1 8,672 1%  
    Number of Slices containing only related logic 1 1 100%  
    Number of Slices containing unrelated logic 0 1 0%  
Total Number of 4 input LUTs 1 17,344 1%  
Number of bonded IOBs 4 250 1%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Apr 5 15:28:08 2017000
Translation ReportCurrentWed Apr 5 15:28:22 2017000
Map ReportCurrentWed Apr 5 15:28:36 2017002 Infos (0 new)
Place and Route ReportCurrentWed Apr 5 15:28:58 2017001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Apr 5 15:29:04 2017006 Infos (0 new)
Bitgen ReportOut of DateTue Apr 4 11:50:42 2017000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentWed Mar 24 09:44:58 2021
WebTalk ReportOut of DateTue Apr 4 11:50:42 2017
WebTalk Log FileOut of DateTue Apr 4 11:50:50 2017

Date Generated: 03/24/2021 - 10:01:11