test Project Status
Project File: Kol_1_zad.xise Parser Errors: No Errors
Module Name: test Implementation State: Placed and Routed
Target Device: xc3s1200e-5fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 2 17,344 1%  
Number of 4 input LUTs 3 17,344 1%  
Number of occupied Slices 2 8,672 1%  
    Number of Slices containing only related logic 2 2 100%  
    Number of Slices containing unrelated logic 0 2 0%  
Total Number of 4 input LUTs 3 17,344 1%  
Number of bonded IOBs 8 250 3%  
Number of BUFGMUXs 1 24 4%  
Number of RPM macros 2      
Average Fanout of Non-Clock Nets 2.50      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Apr 13 09:47:38 2018000
Translation ReportCurrentFri Apr 13 09:47:44 2018000
Map ReportCurrentFri Apr 13 09:47:48 2018002 Infos (0 new)
Place and Route ReportCurrentFri Apr 13 09:48:00 2018002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Apr 13 09:48:02 2018006 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentTue May 11 14:24:33 2021

Date Generated: 05/11/2021 - 16:44:11