| test Project Status | |||
| Project File: | Kol_1_zad.xise | Parser Errors: | No Errors |
| Module Name: | test | Implementation State: | Placed and Routed |
| Target Device: | xc3s1200e-5fg320 |
|
No Errors |
| Product Version: | ISE 14.7 |
|
No Warnings |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
All Constraints Met |
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 2 | 17,344 | 1% | ||
| Number of 4 input LUTs | 3 | 17,344 | 1% | ||
| Number of occupied Slices | 2 | 8,672 | 1% | ||
| Number of Slices containing only related logic | 2 | 2 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 2 | 0% | ||
| Total Number of 4 input LUTs | 3 | 17,344 | 1% | ||
| Number of bonded IOBs | 8 | 250 | 3% | ||
| Number of BUFGMUXs | 1 | 24 | 4% | ||
| Number of RPM macros | 2 | ||||
| Average Fanout of Non-Clock Nets | 2.50 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Fri Apr 13 09:47:38 2018 | 0 | 0 | 0 | |
| Translation Report | Current | Fri Apr 13 09:47:44 2018 | 0 | 0 | 0 | |
| Map Report | Current | Fri Apr 13 09:47:48 2018 | 0 | 0 | 2 Infos (0 new) | |
| Place and Route Report | Current | Fri Apr 13 09:48:00 2018 | 0 | 0 | 2 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Fri Apr 13 09:48:02 2018 | 0 | 0 | 6 Infos (0 new) | |
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | Tue May 11 14:24:33 2021 | |