`timescale 1ns/100ps
module up_counter (
out , // Output of the counter 
enable , // enable for counter
clk , // clock Input 
reset // reset Input 
);

output [7:0] out;
input enable, clk, reset;
reg [7:0] out;
always @(posedge clk) if (reset) out <= 8'b0 ;
else if (enable) out <= out + 1;
endmodule