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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:25:39 05/14/2021 
-- Design Name: 
-- Module Name:    mux2g - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux2g is

	port (
		 a,b,s : in BIT;
		 y : out BIT);

end mux2g;

architecture Behavioral of mux2g is

	begin
	mux2g: process (a, b, s)
	begin
		if (s = '0') then
			y <= a;
		else
			y<=b;
		end if;
	end process mux2g;
end Behavioral;